A gate in front of each input passes it only while the enable is high. The latch then answers S and R only while EN is high and holds its level the rest of the time.
Hint
Put a NAND gate in front of each input of the drawn latch, one taking S and EN and the other R and EN. Their outputs go low only while EN is high. EN can reach both gates on metal 2.
Solution
This is the game's reference drawing for the puzzle. It meets the goal and passes the design rules. Other drawings can pass as well.
Top View of the solved die, captured from the game. Paths that carry a high level at the moment shown are lit. The Side View below cuts through the row between the dashed lines.The whole game window in Isometric View. The scope on the right compares each output with its target band, and the message above it confirms that the drawing passes.The solution on the grid. Squares are numbered from the top left corner, so you can count them. The dashed outline marks the squares you draw, change, or erase; the rest is drawn when the puzzle opens.
Legend
Metal176 squares
Polysilicon83 squares
Contact40 squares
N active32 squares
P active64 squares
N well140 squares
Metal 271 squares
Via9 squares
Input padS, EN, R
Output padQ
Supply padVDD
Ground padGND
Squares you draw, change, or erase155 squares
About the drawing
The drawing uses 367 of the die's 456 squares.
Part of the drawing is in place when the puzzle opens. To finish it, paint 135 empty squares and change 20 drawn squares.
It forms 16 transistors: 8 N transistors and 8 P transistors. Each one is a place where polysilicon crosses active silicon.
40 contacts join metal to the polysilicon or active silicon under it.
9 vias join metal 2 to the metal under it.
The drawing when the puzzle opens. The dashed outline marks the squares the solution changes.