Circuits: VLSI

Walkthrough

Puzzle solutions

The 100 campaign puzzles of Circuits: VLSI, in 10 chapters. Each page gives the goal, the concepts the puzzle introduces, the guide steps, and the hints, followed by the reference drawing that solves the puzzle.

Spoiler note

These pages show the complete solution to every puzzle. On each page the hints come before the solution, so you can stop reading before you reach it.

Chapter 1

Wires on a die

Puzzles 1 to 10

  1. 1A metal pathConnect pad A to pad Y with metal so that Y shows the same signal as A.
  2. 2One input, two outputsConnect A to both Y and Z. Both outputs must show the signal from A.
  3. 3Two separate signalsConnect A to Y and B to Z, and keep the two paths apart.
  4. 4Polysilicon and contactsConnect A to Y. This puzzle offers only Polysilicon and Contact.
  5. 5Crossing pathsConnect A to Y and B to Z. The two paths must cross without joining.
  6. 6Resistance in squaresMake Y read one third of the 5 V supply, about 1.7 V.
  7. 7Wires take timeMake Y follow A about 6 ns late, as the target shows.
  8. 8Short crossingsConnect A to Y, B to Z, and C to W. Every output must follow its input within about a third of a nanosecond of the target.
  9. 9A wide stripConnect A to Y with polysilicon so that Y follows A as quickly as the target. This puzzle offers only Polysilicon and Contact.
  10. 10Four equal stepsMake Y read 3.75 V, Z read 2.5 V, and W read 1.25 V: the supply divided into four equal steps.

Chapter 2

Transistors in silicon

Puzzles 11 to 20

  1. 11A switch made by crossingMake Y follow A only while C is high.
  2. 12P transistors need a wellMake Y follow A only while C is low.
  3. 13Finish the inverterMake Y the inverse of A. The top half is drawn: add the N transistor that pulls Y down to GND.
  4. 14CMOS inverterMake Y the inverse of A: high while A is low, and low while A is high.
  5. 15Balanced edgesDraw the P transistor so that Y rises as fast as it falls.
  6. 16A strong outputY now drives a large load. Widen the transistors so that both edges are at least as fast as the target.
  7. 17Two inverters make a bufferMake Y follow A through two inverters in a row.
  8. 18A slow fallMake Y fall about four times more slowly than it rises, as the target shows. The inverter is drawn.
  9. 19Repair an inverterThis inverter breaks three design rules. Correct the drawing so that the rule list is empty and Y is the inverse of A.
  10. 20An inverter on its sideMake Y the inverse of A. Here VDD runs down the left edge, GND down the right edge, A enters at the top, and Y leaves at the bottom.

Chapter 3

Logic gates

Puzzles 21 to 30

  1. 21A NAND gateMake Y low only while A and B are both high. For every other pair of inputs Y is high.
  2. 22A NOR gateMake Y high only while A and B are both low.
  3. 23AND from NANDMake Y high only while A and B are both high. The NAND gate is drawn: add an inverter after it.
  4. 24An OR gateMake Y high while A or B is high. The inputs arrive at pads on the top edge, above the VDD rail.
  5. 25Three inputsMake Y low only while A, B, and C are all high.
  6. 26A strong NANDY now drives a large load. Widen the transistors so that both edges are at least as fast as the target.
  7. 27A and not BMake Y high only while A is high and B is low.
  8. 28Two gates, one pair of inputsMake Y the NAND of A and B, and Z their NOR. The NAND gate is drawn.
  9. 29Read the targetMake Y match its target. The goal does not name the gate: compare the target with A and B on the scope to find when Y is high.
  10. 30AND and OR togetherMake Y high while A and B are both high, or while C is high.

Chapter 4

Compound gates

Puzzles 31 to 40

  1. 31An AND-OR-INVERT gateMake Y low while A and B are both high, or while C is high. Build it as one gate.
  2. 32An OR-AND-INVERT gateMake Y low while A or B is high and C is also high.
  3. 33Two pairsMake Y low while A and B are both high, or while C and D are both high.
  4. 34Gate orderMake Y low while B is high, or while A and C are both high. The die is narrow: draw each strip across all three gate lines without a break.
  5. 35Exclusive ORMake Y high while A and B differ. The compound gate and two inverters are drawn: connect them.
  6. 36A multiplexerMake Y follow B while S is high, and A while S is low. The inverter for S and an output inverter are drawn.
  7. 37MajorityMake Y high while at least two of A, B, and C are high.
  8. 38An extra squareY should be low while A or B is high and C is also high. One square joins two nets that should be apart: find it and remove it.
  9. 39A strong compound gateY now drives a large load. Widen the transistors so that both edges are at least as fast as the target.
  10. 40A smaller exclusive ORMake Y high while A and B differ. The die has room for two rows of cells that share the GND rail.

Chapter 5

Switches

Puzzles 41 to 50

  1. 41A transmission gateMake Y follow A at full level while C is high, and keep its last level while C is low. CN is always the inverse of C.
  2. 42One control signalMake Y follow A while C is high, and keep its last level while C is low. This time there is no CN pad: make the inverse of C on the die.
  3. 43A two-way switchMake Y follow A while S is low and B while S is high. SN is always the inverse of S.
  4. 44Choose an outputMake Y follow A while S is low, and Z follow A while S is high. The output that is not chosen must be low.
  5. 45Letting go of a lineMake Y the inverse of A while E is high. While E is low, Y must keep its last level.
  6. 46One line, two driversMake Y the inverse of A while S is low, and the inverse of B while S is high. The two drivers share the line Y.
  7. 47Exclusive OR from switchesMake Y high while exactly one of A and B is high.
  8. 48A dynamic gateWhile CLK is low, Y must be high. While CLK is high, Y falls when A and B are both high, and then stays low until CLK falls, even if A or B falls first.
  9. 49DominoWhile CLK is low, Y must be low. While CLK is high, Y rises when A, B, and C are all high, and then stays high until CLK falls.
  10. 50Swapped controlsRepair the drawing so that Y follows A while S is low and B while S is high. One of the two transmission gates has its controls the wrong way around.

Chapter 6

Speed

Puzzles 51 to 60

  1. 51A delay lineMake Y follow A about 7 ns late, as the target shows.
  2. 52FingersY drives a 10 pF load. Make Y the inverse of A, with edges at least as fast as the target.
  3. 53Arrive togetherY drives 2 pF and Z drives 8 pF. Make both the inverse of A, and make them switch at the moment the targets show.
  4. 54A pulse on each riseMake Y give a pulse about 6 ns long each time A rises, and stay low the rest of the time.
  5. 55A ring oscillatorClose the ring so that Y repeats with a period between 10 and 16 ns once EN is high.
  6. 56An even ringThe ring of four stages does not repeat. Make Y repeat with a period between 10 and 22 ns once EN is high.
  7. 57A slower ringMake Y repeat with a period between 22.5 and 27 ns once EN is high.
  8. 58Tune the periodMake Y repeat with a period between 15.3 and 17.2 ns once EN is high.
  9. 59Growing stagesY now drives 8 pF. Make Y swing fully at the ring's period, and keep the period between 17.5 and 20 ns.
  10. 60Two phasesMake Y high while CLK is low and Z high while CLK is high, with a short gap at each change so that they are never high together.

Chapter 7

A second metal layer

Puzzles 61 to 68

  1. 61Metal 2 and viasConnect A to Y and B to Z. The two paths must cross without joining; cross them on metal 2.
  2. 62Faster than polysiliconConnect A to Y across the two wide rails. Y drives a large load and must follow A as closely as the target.
  3. 63Over the cellMake Y the inverse of A, and connect B to Z. The inverter is drawn, and the path from B to Z must cross it.
  4. 64Reverse three linesReverse the order of the three lines: make Y follow C, Z follow B, and W follow A.
  5. 65Supply strapsMake Y the inverse of A and Z the inverse of B. The VDD pad reaches only the upper VDD rail, and the GND pad only the lower GND rail.
  6. 66One via too manyMake Y follow A, Z follow B, W follow C, and X follow D. The routing is drawn, but one via joins two signals.
  7. 67Inputs from aboveMake Y low only while A and B are both high. The NAND gate is drawn, and its pads sit in a row on the top edge, above the VDD rail.
  8. 68A block of two gatesMake Y the NAND of A and B, and Z their NOR. Both gates are drawn: wire each input to both gates, and each output to its pad.

Chapter 8

Memory

Puzzles 69 to 80

  1. 69A set and reset latchMake Q go high when S is high and low when R is high, and keep its level while S and R are both low.
  2. 70A latch from NAND gatesMake Q go high when SN is low and low when RN is low, and keep its level while SN and RN are both high.
  3. 71Both outputsMake Q go high when S is high and low when R is high, and make QN its inverse. While S and R are both high, Q and QN are both low.
  4. 72A latch with an enableMake Q go high when S is high and low when R is high, but only while EN is high. While EN is low, Q keeps its level whatever S and R do.
  5. 73A data latchMake Q follow D while EN is high. While EN is low, Q keeps the level D had when EN fell.
  6. 74A latch from switchesMake Q follow D while EN is high. While EN is low, Q keeps the level D had when EN fell.
  7. 75A weak feedback inverterMake Q follow D while EN is high, and keep its level while EN is low. The feedback inverter in the drawing is too strong for the switch to overpower.
  8. 76A memory cellMake Q take the level of BL each time WL is high, and keep it while WL is low. BLN is always the inverse of BL.
  9. 77An edge-triggered flip-flopMake Q take the level of D at each rising edge of CLK and keep it until the next rising edge. Changes of D between rising edges do not reach Q.
  10. 78Divide by twoMake Q change level at every rising edge of CLK, so that it repeats every two clock periods. Only the period of Q is judged.
  11. 79A reset on the clockMake Q change level at every rising edge of CLK, except that a rising edge while R is high makes Q low.
  12. 80A shift registerMake Q1 take the level of D at each rising edge of CLK, and Q2 take the level Q1 had just before the same edge.

Chapter 9

Arithmetic

Puzzles 81 to 90

  1. 81A half adderAdd A and B: make S high while exactly one of them is high, and CO high while both are. The carry is drawn: add the sum.
  2. 82Three-input exclusive ORMake Y high while an odd number of A, B, and C are high: one of them, or all three. The exclusive OR of A and B is drawn.
  3. 83A full adderAdd A, B, and CI. S is drawn and is high while an odd number of them are high: make CO high while at least two of them are high.
  4. 84Equal bitsMake Y high while A and B are equal: both high or both low.
  5. 85Two-bit equalityMake Y high while the number A1 A0 equals B1 B0, that is, while A1 equals B1 and A0 equals B0. The comparison of A0 with B0 is drawn.
  6. 86Greater thanMake Y high while the number A1 A0 is greater than B1 B0. The majority gate and the inverter that drives Y are drawn.
  7. 87A decoderMake one output high for each value of A1 A0: Y0 while it is 00, Y1 while it is 01, Y2 while it is 10, and Y3 while it is 11.
  8. 88A half subtractorSubtract B from A: make Y high while A and B differ, and BO high while A is low and B is high. The drawing is a half adder, so BO is wrong.
  9. 89A parity treeMake Y high while an odd number of A, B, C, and D are high, at least as fast as the target. Three exclusive OR gates are drawn: wire them.
  10. 90A ripple carryAdd CI to the number A1 A0: make S1 S0 the two-bit sum, and CO high while the sum is four. The half adder for bit 0 is complete, and the one for bit 1 is drawn.

Chapter 10

Small machines

Puzzles 91 to 100

  1. 91A ripple counterMake Q1 and Q0 count 0, 1, 2, 3 and repeat, one step on each rising edge of CLK, with Q0 as the low bit. Both flip-flops already toggle; the second one has no clock yet.
  2. 92One clock for both bitsMake Q1 and Q0 count 0, 1, 2, 3 and repeat, with both flip-flops on CLK. Q0 already toggles; give D1 the next value of Q1.
  3. 93A twisted ringMake Q0 and Q1 step through 00, 10, 11, 01 and repeat: on each rising edge of CLK, Q0 takes the inverse of Q1 and Q1 takes Q0.
  4. 94Load or holdMake Q take the value of A on a rising edge of CLK while EN is high, and keep its value while EN is low.
  5. 95Divide by threeMake Q0 high for one clock period in every three, and Q1 follow Q0 one clock period later.
  6. 96Two ones in a rowMake Y high while the last two values of A taken on rising edges of CLK were both high.
  7. 97Every fourth clockMake Y high for one clock period in every four, while the count on Q1 and Q0 is 1.
  8. 98Count to three and stopMake Q1 and Q0 count 0, 1, 2, 3 on rising edges of CLK and then stay at 3.
  9. 99An odd number of onesMake Q high while an odd number of the values of A taken on rising edges of CLK were high.
  10. 100Three outputs in turnMake X high for two clock periods, then Y for one, then Z for one, and repeat.