A ring of inverting stages
A ring of an odd number of inverting stages never settles: each stage changes the next, and the change comes back inverted. The period is twice the time a change takes to go around the ring.
Puzzle 55 of 100
Close the ring so that Y repeats with a period between 10 and 16 ns once EN is high.
A ring of an odd number of inverting stages never settles: each stage changes the next, and the change comes back inverted. The period is twice the time a change takes to go around the ring.
A NAND gate in the ring inverts its ring input only while EN is high. While EN is low its output stays high, so the ring rests in a known state at power on and starts when EN rises.
The NAND gate and the two inverters after it become a ring of three inverting stages when the second inverter's output returns to the NAND gate's free input. Take that output down under the GND rail on polysilicon, along the row below on metal, and back up into the free gate line.
This is the game's reference drawing for the puzzle. It meets the goal and passes the design rules. Other drawings can pass as well.

