Two phases
Circuits that pass data from one stage to the next often need two clock phases that are never high together. Gating a clock with a delayed copy of itself leaves a gap at each edge as long as the delay.
Puzzle 60 of 100
Make Y high while CLK is low and Z high while CLK is high, with a short gap at each change so that they are never high together.
Circuits that pass data from one stage to the next often need two clock phases that are never high together. Gating a clock with a delayed copy of itself leaves a gap at each edge as long as the delay.
Each chain gives a late copy of CLK. Y is the NOR of CLK and its copy, so it rises only after the copy falls; Z is the AND of the two, from a NAND gate and an inverter, so it rises only after the copy rises.
This is the game's reference drawing for the puzzle. It meets the goal and passes the design rules. Other drawings can pass as well.

