A memory cell is two inverters in a ring with an N switch on each side. When the word line is high, both switches conduct. While the word line is low, the ring keeps its bit.
Two bit lines
An N switch passes a low well but a high poorly. The cell is written from both sides, with BL and BLN at opposite levels, and the side that goes low decides.
Hint
Add an N transistor from BL to Q and another from BLN to the other node of the cell, both with their gates on WL. The bit line that is low pulls its side of the cell down, and the inverters do the rest.
Solution
This is the game's reference drawing for the puzzle. It meets the goal and passes the design rules. Other drawings can pass as well.
Top View of the solved die, captured from the game. Paths that carry a high level at the moment shown are lit. The Side View below cuts through the row between the dashed lines.The whole game window in Isometric View. The scope on the right compares each output with its target band, and the message above it confirms that the drawing passes.The solution on the grid. Squares are numbered from the top left corner, so you can count them. The dashed outline marks the squares you draw, change, or erase; the rest is drawn when the puzzle opens.
Legend
Metal80 squares
Polysilicon28 squares
Contact12 squares
N active17 squares
P active9 squares
N well39 squares
Metal 216 squares
Via3 squares
Input padWL, BL, BLN
Output padQ
Supply padVDD
Ground padGND
Squares you draw, change, or erase30 squares
About the drawing
The drawing uses 144 of the die's 209 squares.
Part of the drawing is in place when the puzzle opens. To finish it, paint 25 empty squares and change 5 drawn squares.
It forms 6 transistors: 4 N transistors and 2 P transistors. Each one is a place where polysilicon crosses active silicon.
12 contacts join metal to the polysilicon or active silicon under it.
3 vias join metal 2 to the metal under it.
The drawing when the puzzle opens. The dashed outline marks the squares the solution changes.